As integrated circuit technology advances, chips have increasingly higher operating speeds, and have widely employed techniques such as double data rate (DDR) and pipelines to achieve higher data throughput. However, operation at higher speeds necessitates stricter requirements for accuracy of time sequencing, which means stricter requirements for the performance of system time clocks, wherein, an important performance index is the duty cycle of the clock. A clock with 50% duty cycle is the most advantageous for data dissemination. For a system that employs a DDR and pipeline operation mode, 50% duty cycle ensures that the data can be established and maintained correctly in the transmission process and ensures normal and stable operation of the system.
In actual applications, the system clock is usually generated by means of a phase locked loop (PLL) or delay locked loop (DLL). In this process, the clock generated after frequency multiplication and synchronization often cannot ensure 50% duty cycle, owing to the mismatch resulting from the circuit design itself and the deviation between the chip manufacturing process and the simulated model. In addition, a duty cycle mismatch of the clock will also occur in the clock transmission process, since there is system and process deviation in the transmission link. Especially in high frequency applications, a duty cycle mismatch may even cause the clock signal to not flip over normally, and thereby result in severe time sequence errors. Therefore, it is necessary to introduce a duty cycle calibration circuit in application scenarios in which the requirement for a duty cycle is very strict.
At present, there are mainly two approaches for duty cycle calibration: a digital approach and an analog approach. The digital approach often cannot achieve an accurate calibration result because it is limited by the minimum delay unit and because the calibration accuracy has a nature of discreteness; in addition, through the digital approach, the operating speed is not high enough owing to the requirement of the time sequence because the digital approach usually utilizes phase synthesis, count detection, etc. There are a variety of methods in an analog approach, with the difference among them mainly lying in the detection mode of the duty cycle. However, compared to the digital approach, most methods in the analog approach can achieve higher duty cycle calibration accuracy, operate at a higher frequency, and obtain smaller edge jitter.